The present invention relates generally to data processing and, in particular, to promoting utilization of the store bandwidth of a banked cache.
A processor of a data processing system is typically supported by one or more levels of cache memory that buffer, in low latency storage, data and instructions likely to be accessed by the processor. To increase memory access bandwidth, caches can be implemented with a banked architecture in which each bank includes its own respective resources, such as queues, a data array, and a cache directory. In such banked caches, memory access requests are distributed among the banks based on selected bits of the addresses referenced by the memory access requests.
The increased memory access bandwidth potentially offered by banked cache architectures is only realized if the addresses referenced by memory access requests are well distributed. If the addresses of a workload are not well distributed but are instead concentrated in the address space associated with a subset of the available banks, the cache can undesirably operate utilizing only a fraction of the available memory access bandwidth.